HBM is a reliability bottleneck, requiring greater visibility into individual bonds and TSVs, and more sophisticated SI/PI ...

Heterogeneous integration does not simply increase complexity but redistributes where quality must be assured.

A smaller set of fiber connectors that meet manufacturing test high insertion count will ease the cost burden for all. Test specifications and associated standardized test formats will facilitate data ...

how data center AI is growing rapidly; how almost everyone says they could grow revenue faster with more compute; and, that there are challenging, stubborn bottlenecks to data center AI growth, ...

An imec researcher published a technical paper titled “Bond Front Velocity in Lubrication-Mediated Bonding of Flexible ...

Researchers from MIT, SLAC, Stanford University, and Argonne National Laboratory published a technical paper titled “Spatiotemporal mapping of anisotropic thermal transport in GaN thin films via ...

SK hynix's $38B new fabs; memory density increases; 2026 chip industry revenue to hit $1.65T; imec metrology roadmap; MIT's ...

Modern system-on-chips (SoCs) are no longer built around a single clock and a single reset. Today’s designs integrate hundreds of IP blocks, multiple power domains, software-controlled reset sequences ...

PCIe is the primary high-speed interconnect used to connect processors with accelerators, memory devices, storage, and networking components. It provides a common and scalable foundation for moving ...

Many security architectures rely on immutable ROM as the first trusted code executed by a processor. It provides a stable foundation for authenticating the rest of the boot chain, but that same ...

This dual challenge — cybersecurity and functional safety—is captured in two landmark standards: ISO 26262 for functional ...

Chip security must be designed in from the start, with clear requirements that connect architecture, verification, software, manufacturing, and field deployment. AI is expanding both the scale and ...