Design-Reuse20d
DDR3 PHY
IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant with JESD79-3 specification. The DDR3 PHY IP provides the Industry ...
Design-Reuse1y
Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
The emerging DDR3 memory standard will extend the performance range of DDR memories considerably, while maintaining some amount of backwards compatibility with the existing DDR2 memory standard. It is ...
GitHub1y
AXI DDR3 SDRAM Memory Controller for Xilinx GoWin Altera Intel Lattice FPGAs, written in Verilog.
Medium-size (about 1300 logic elements, when targeting LUT4-based FPGAs), and medium-speed (upto 125 MHz, 250 Mbps, per DQ-pin), DDR3 controller that operates ... when they refer to the same memory ...