HBM is a reliability bottleneck, requiring greater visibility into individual bonds and TSVs, and more sophisticated SI/PI ...

Heterogeneous integration does not simply increase complexity but redistributes where quality must be assured.

A smaller set of fiber connectors that meet manufacturing test high insertion count will ease the cost burden for all. Test specifications and associated standardized test formats will facilitate data ...

how data center AI is growing rapidly; how almost everyone says they could grow revenue faster with more compute; and, that there are challenging, stubborn bottlenecks to data center AI growth, ...

AI has pushed security to the forefront, helping attackers find vulnerabilities in chips and the chip industry to defend against them. Security needs to extend throughout a chip’s lifetime, but it’s ...

Both approaches scale toward packages as large as 240 mm x 240 mm, with a roadmap extending beyond 12x reticle integration ...

An imec researcher published a technical paper titled “Bond Front Velocity in Lubrication-Mediated Bonding of Flexible ...

Modern system-on-chips (SoCs) are no longer built around a single clock and a single reset. Today’s designs integrate hundreds of IP blocks, multiple power domains, software-controlled reset sequences ...

Compute clusters offer more processing capacity but at the cost of higher power. Software is needed to allocate resources ...

As packages get larger and thinner, warpage is becoming a process-control problem rather than a simple flatness spec.

On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed ...