EDN

System Verilog configurable coverage model in an OVM setup – concept of reusability

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...
Design-Reuse

System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability

Verification – has been becoming a nightmare for engineers with the increasing requirements and complexity of the design. Mitigating the complexity of a verification environment with the increasing ...
Design-Reuse

Reusing Verilog IP Cores in SystemC Environment by V2SC

SystemC 2.1 supports all hardware concepts introduced by HDLs such as Verilog and VHDL. V2SC proposes a methodology for automatic conversion of Verilog 2001 constructs into SystemC 2.1 language. This ...