Design-Reuse

Actel's Libero IDE Delivers Unmatched Value, Flexibility and Efficiency for Complex FPGA-Based Designs

New Static Timing Analysis Engine and Expanded Third-Party Support Enable Designers to Meet Timing Closure and Achieve Higher Performance MOUNTAIN VIEW, Calif., July ...
Design-Reuse

Actel Strengthens Libero Integrated Design Environment for Next-Generation FPGA Designs

SUNNYVALE, Calif., February 12, 2003 - Actel Corporation (Nasdaq: ACTL), a supplier of innovative programmable logic solutions, today announced it has enhanced its Actel Liberoâ„¢ integrated design ...
EDN

Actel’s Libero With SmartTime Available

Citing significant new functionality for design analysis and timing closure, Actel unveiled its Libero version 6.2 Integrated Design Environment (IDE) for FPGA design engineers. The new version ...
EDN

Actel upgrades FPGA design tool bundle

SAN MATEO, Calif. Actel Corp. has released an upgrade to its Libero FPGA design environment with new ease-of-use and run-time enhancement features. The Libero tool bundle includes Actel's internally ...
Electronic Design

IDE Enhances Synthesis For Next-Generation FPGA Designs

Targeted for the design and development of Actel's FPGA families, the Libero 2.3 integrated development environment (IDE) upgrades the synthesis and place-and-route tools from Synplicity and Actel, ...