Design-Reuse4y
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs ... The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.
Design-Reuse4y
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
The Controller IP is silicon proven and connects to DDR PHY via the DFI 4.0 interface to provide customers a complete memory interface solution with ease of integration and faster time to market ...